Accumulation mode field-effect transistors, sometimes referred to as "ACCUFETs", are trench-type MOSFETs which contain no body region and hence no PN junctions. The region between the trenched gates, sometimes called a "mesa", is made relatively narrow (e.g., 0.5 to 4.0 .mu.m wide), and the gate material (typically polysilicon) is doped in such a way that it has a work function which depletes the entire mesa region, much like a junction field-effect-transistor (JFET). The current path extends between a "source" at the top of the mesa and a "drain" at the bottom of the substrate. The trenches are normally formed entirely in an epitaxial layer which is grown on top of the substrate.
A cross-sectional view of a typical ACCUFET 10 is illustrated in FIG. 1. Trenched gates 11 are etched in a silicon material 12, which includes an N-epitaxial layer 13 grown on an N+ substrate 14. Trenched gates 11 define two cells 10A and 10B. An N+ source 15 is formed at the top of the mesa between gates 11. A metal layer 16 is formed over the source regions, and a power source 17 and a load 18 are connected between the N+ source 15 and the N+ substrate 14, which acts as the drain.
ACCUFET 10 is turned off when the gate voltage is equal to the source voltage (i.e., V.sub.gs =0). If V.sub.gs is increased, the depletion regions surrounding the gates (shown by the dashed lines) contract and open a current path between the source and the drain. With further increasing V.sub.gs the depletion regions continue to contract until eventually accumulation regions are formed adjacent the trenches, enhancing channel conduction and further lowering the on-resistance of the device.
This sequence of events is illustrated in FIGS. 2A, 2B and 2C, FIG. 2A showing ACCUFET 10 in the off condition, FIG. 2B showing ACCUFET 10 turned partially on, and FIG. 2C showing ACCUFET 10 turned fully, with the accumulation regions being designated by the numeral 19. In FIGS. 2B and 2C the arrows represent the flow of electrons from the source to the drain.
Additional information concerning ACCUFETs is given in U.S. Pat. No. 4,903,189 to Ngo et al.; B. J. Baliga et al., "The Accumulation-Mode Field-Effect Transistor: A New Ultralow On-Resistance MOSFET", IEEE Electron Device Letters, Vol. 13, No. 8, August 1992, pp. 427-429; and T. Syau et al., "Comparison of Ultralow Specific On-Resistance UMOSFET Structures: The ACCUFET, EXTFET, INVFET, and Conventional UMOSFET's", IEEE Electron Device Letters, Vol. 41, No. 5, May 1994, pp. 800-808, each of which is incorporated herein by reference in its entirety.
ACCUFETs can be fabricated with a very high cell density and a very low on-resistance. Despite these advantages, ACCUFETs have not so far achieved widespread use in the field of power semiconductor devices for several reasons. One of the principal reasons is their inability to withstand high voltages when they are in an off condition.
This problem is illustrated in FIGS. 3A and 3B, which show oxide layers 11A bordering gates 11. FIG. 3A shows ACCUFET 10 connected to an inductive load 30. The symbols t.sub.0, t.sub.1, t.sub.2, t.sub.3 and t.sub.4 represent sequential times in the process of turning off ACCUFET 10. The dashed lines in FIG. 3A represent the edges of the spreading depletion region at times t.sub.0, t.sub.1, t.sub.2, t.sub.3 and t.sub.4. FIG. 3B illustrates the strength of the electric field in the gate oxide layer 11A and epitaxial layer 13 at times t.sub.0, t.sub.1, t.sub.2, t.sub.3 and t.sub.4. As shown, as V.sub.gs begins to decrease at time t.sub.0, the electric field resides in the gate oxide layer 11A and a portion of epitaxial layer 13. At times t.sub.1 and t.sub.2, the strength of the field in the gate oxide layer 11A has increased somewhat, but a portion of the increase is absorbed by the epitaxial layer 13. At time t.sub.2, however, the electric field has reached the interface between epitaxial layer 13 and N+ substrate 14. Since N+ substrate 14 is heavily doped, it cannot support an electric field to any significant extent, and thus all further increases in the field must be taken up in the limited space of gate oxide layer 11A and epitaxial layer 13. This means that the electric field in the gate oxide layer 11A begins to increase at a faster rate with decreases in V.sub.gs. Unless limited in some way, the increases may eventually rupture gate oxide layer 11A, and in FIG. 3B this is shown as occurring at time t.sub.4. When the gate oxide layer has been ruptured, the device is generally destroyed beyond repair.
Since many loads (such as load 30) include an inductive component, voltage spikes inevitably occur in the power lines as the loads are switched on and off. The inability of ACCUFETs to withstand these voltage spikes has seriously limited their use in the power MOSFET field.
Push-pull halfbridge circuit 40, shown in FIG. 4A, illustrates the problem that occurs when using ACCUFETs with an inductive load. Halfbridge circuit 40 includes a high-side ACCUFET 41 and a low-side ACCUFET 42, which drive a coil 43 in a motor, for example. ACCUFETs 41 and 42 are connected in series between a battery voltage V.sub.batt and ground. FIG. 4B shows the voltages (V.sub.GS) across the gate oxides of the ACCUFETs 41 and 42 and the voltage V.sub.o at the output of the halfbridge circuit. Assume that at a starting point, V.sub.o is low, meaning that high-side ACCUFET 41 is off and low-side ACCUFET 42 is on. With ACCUFET 42 on, generally some current will be flowing through ACCUFET 42 and coil 43. In this situation the gate of ACCUFET 42 is tied to V.sub.batt and the gate of ACCUFET 41 is tied to a voltage equal to V.sub.o, so that the V.sub.GS in ACCUFET 41 is zero.
In order to switch V.sub.o from low to high, low-side ACCUFET 42 is turned off and then high-side ACCUFET 41 is turned on. Both ACCUFETs cannot be on at the same time, however, or a direct current path from V.sub.batt to ground would be created, leading to a large current and most likely the destruction of both devices. Thus, at time T.sub.1 in FIG. 4B, ACCUFET 42 is turned off by switching its gate voltage from V.sub.batt to ground. However, current flowing through coil 43 resists an abrupt cutoff, and V.sub.o therefore increases rapidly to a level greater than V.sub.batt, as shown by the top curve in FIG. 4B. V.sub.o will increase until ACCUFET 42 either breaks down or is destroyed. Meanwhile, the V.sub.GS in ACCUFET 41 falls rapidly at an equal rate (its source being biased more positively than its gate). It is highly likely that in this situation the gate oxide of ACCUFET 41 will rupture before ACCUFET 42 begins to conduct and thereby attempt to clamp the output voltage V.sub.o.
A scenario similar to that shown in FIGS. 4A-4B will occur in virtually any situation in which an ACCUFET is used to switch currents through an inductive load.
Accordingly, there is a real need for a device which has the superior cell density and on-resistance characteristics of an ACCUFET yet is able to switch an inductive load or survive voltage spikes of limited energy in a reliable manner particularly without damaging the trench gate.